The present invention relates generally to semiconductor device processing and more particularly to apparatus and methods for determining floating body effects such as hysteretic propagation delays in SOI devices.
A continuing trend in the semiconductor manufacturing industry is toward smaller and faster transistor devices, which consume less power. Toward that end, device scaling is a continuous design goal, wherein device features sizes and spaces are reduced. However, performance limits arc reached in technologies where scaled transistors and other electrical devices are formed directly in a wafer substrate, such as silicon. These are sometimes referred to as bulk devices. To surpass the performance limitations of bulk devices, recent scaling efforts have included the use of silicon over oxide (SOI) wafers, in which a silicon layer overlies an insulator layer above a silicon substrate. SOI wafers may be fabricated according to known SOI wafer manufacturing techniques, such as SIMOX, bond-and-etch-back and smart-cut technology.
In SOI wafers, the active semiconductor regions of the wafer are formed in the silicon on top of the oxide insulator, whereby these active regions are electrically isolated from one another. This technique achieves certain design advantages, such as a significant reduction in parasitic capacitances that exist in non-SOI (bulk) devices, as well as enhanced resistance to radiation damage. Partially depleted SOI devices are produced using one type of SOI process in which the transistors are formed in a deposited semiconductor layer which is thick enough that the channel region will not be fully depleted through its full thickness when the device is in operation. The transistor design and operation in partially depleted SOI processes are similar to that of bulk CMOS devices.
Although SOI designs provide certain advantages over bulk designs, SOI devices suffer from certain effects related to the isolation of the active devices from the substrate material underlying the oxide layer, which are sometimes referred to as floating-substrate or floating body effects. In bulk transistors, the transistor body may be electrically connected through the substrate. In this case, the transistor body is at a relatively fixed potential, and consequently, the transistor threshold voltage is stable relative to the drain-to-source voltage. In many SOI transistors however, the body (e.g., the undepleted silicon under the gate) is electrically floating with respect to the substrate because of the intervening oxide insulator layer. Thus, when sufficient drain-to-body bias is applied to the transistor, impact ionization can generate electron-hole pairs near the drain. These electron-hole pairs cause a voltage differential to build up between the body node and the source of the transistor because majority carriers travel to the body while the minority carriers travel to the drain. The resulting voltage differential lowers the effective threshold voltage, thereby increasing the drain current.
The isolated body creates capacitive coupling between the body and the gate, between the body and the source, and between the body and the drain, in addition to diode couplings between the body and the source and between the body and the drain. These effects bias the body, creating a variation in the transistor threshold voltage during switching which is dependent upon the current and past states of the transistor. During switching, these effects bias the body through two mechanisms; capacitive coupling between the body and the gate, source, and drain, as well as charging and discharging between the body and the source and drain through diode coupling. This history dependent operation, sometimes referred to as hysteretic behavior, results from potentially large uncertainties in the floating body potential and, thus, uncertainties in the threshold voltage of devices due to unknown switching history.
These floating body effects can contribute to undesirable performance shifts in the transistor relative to design, as well as to increased instability of the transistor operating characteristics. In order to address these SOI floating body issues, some designs provide for electrical connection of the body or the source of an SOI transistor to the substrate. Transistors formed in this manner in an SOI wafer are sometimes referred to as tied body transistors. Although this technique serves to prevent body charging by creating a direct contact to the substrate, implementation of this approach complicates the device manufacturing process and also increases area overhead because tied body devices consume a larger area than floating body devices. Thus, most SOI designs must take these floating body effects into account.
Because these and other floating body issues affect end-product device performance, monitoring the hysteretic behavior of SOI devices is needed to refine and monitor the SOI manufacturing process. Thus, it is desirable to measure floating body effects in wafers at various points in a manufacturing process flow. One measure of the veracity of an SOI process is the propagation delays in switching a floating body transistor from one state to another. The threshold voltage of such floating body devices is dependent upon the body potential. The body potential, in turn, is dependent upon the current and past states of the transistor (e.g., the voltages at the various terminals of the device). Thus, the propagation delays are often measured at various voltages with switching signals of varying amounts of preconditioning, to obtain a curve of average propagation delay vs. time.
Typically, these measurements are obtained manually on a test bench, using oscilloscopes and high frequency probes to monitor floating body transistor switching delays under various conditions. Pulse generators are connected to the inputs of inverters or other floating body devices, which are formed of floating body MOS transistors, and the device outputs are monitored using the oscilloscope. Such testing is time consuming, and ill fitted for testing every wafer in a high throughput production setting. Thus, there is a need for improved apparatus and methods for measuring hysteretic propagation delay in SOI devices, which are amenable to automation using readily available, inexpensive test equipment.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention relates to apparatus and methodologies which may be employed to determine hysteretic propagation delay and other floating body effects in SOI devices.
In accordance with one aspect of the invention, test apparatus is provided, which comprises a plurality of floating body devices fabricated in series with one another in the wafer, and having an input for receiving an input pulse edge and an output for providing a propagated pulse edge associated with propagation of the input pulse edge through the chain of floating body devices. The apparatus further comprises a pulse generation circuit, which receives the input pulse edge and the propagated pulse edge, and provides a pulse output corresponding to a delay time associated with the floating body chain according to the input pulse edge and the propagated pulse edge. The width of the pulse output may be representative of the propagation delay of the floating body chain, such as provided by an exclusive-OR gate receiving the input pulse edge and the propagated pulse edge as inputs. The apparatus may further comprise an integrator receiving and integrating the pulse output to provide an integral output having an amplitude corresponding to the floating body chain delay.
Another aspect of the invention provides test systems for determining floating body effects in an SOI wafer, comprising a plurality of floating body devices fabricated in series with one another in the wafer, and a pulse generation circuit, which receives the input pulse edge and the propagated pulse edge, and provides a pulse output corresponding to a delay time associated with the floating body chain. The system further includes a tester comprising means for providing the input pulse edge to the input of the floating body chain, such as a pulse generator, means for sensing the pulse output from the pulse generation circuit, such as a volt meter, and means for determining at least one floating body delay according to the pulse output, such as a processor.
In accordance with still another aspect of the invention, test methods are provided, comprising providing a pulse edge to a floating body chain comprising a plurality of series connected floating body devices in the SOI wafer, providing a pulse output corresponding to a delay time associated with the floating body chain according to the input pulse edge and a propagated pulse edge, and determining a floating body delay value according to the pulse output. The determination of the floating body delay value may comprise integrating the pulse output to provide an integral value, and determining the floating body delay value according to the integral value.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.